Many existing Static Random Access Memory devices (SRAMs) share a common problem of slow access time whenever a read follows a write in the same column. A schematic diagram of one column of a typical Bi-CMOS SRAM is shown in FIG. 1. Devices Q1 and Q2 are the bit-line load devices which bias the bit-lines near VCC. Devices R1 and R2 are bit-line load resistors which set the voltage swing on the bit-lines during a read access.
Devices G1 and G2 disable Q1 or Q2 during a write. During a read, the bases of Q1 and Q2 are driven to VCC. During a write, one of the bit-lines is driven to GND, while the other is left near VCC. Because of this, a read following a write in the same column requires additional time (as compared to consecutive reads) for the bit-lines to be equalized before the state of the accessed memory bit can be sensed. What is needed is a method for reducing the write recovery time.